Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs
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Abstract
The accuracy of the split-CV mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a Al2O3 gate dielectric and an InP barrier, through a "simulated experiment" procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental I-V and CV curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split-CV method can appreciably underestimate the actual channel mobility in these devices, with an error of > 20% and > 50% on peak mobility and high-VGS mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing VGS. It is shown that this behavior can be an artifact of the extraction method, which may mask physical mechanisms causing a real mobility drop with decreasing channel carrier density, such as Coulomb scattering mechanisms. This poses limitations to the adoption of split-C V mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V FETs, including both heterostructure-based and inversion-mode devices.
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<record><TEI><teiHeader><fileDesc><titleStmt><title xml:lang="en" level="a">Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs</title><author><name sortKey="Morassi, Luca" uniqKey="Morassi L">Luca Morassi</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Engineering Sciences and Methods, University of Modena and Reggio Emilia</s1><s2>42122 Reggio Emilia</s2><s3>ITA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ></inist:fA14><country>Italie</country><wicri:noRegion>42122 Reggio Emilia</wicri:noRegion></affiliation></author><author><name sortKey="Verzellesi, Giovanni" uniqKey="Verzellesi G">Giovanni Verzellesi</name><affiliation wicri:level="1"><inist:fA14 i1="01"><s1>Department of Engineering Sciences and Methods, University of Modena and Reggio Emilia</s1><s2>42122 Reggio Emilia</s2><s3>ITA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ></inist:fA14><country>Italie</country><wicri:noRegion>42122 Reggio Emilia</wicri:noRegion></affiliation></author><author><name>HAN ZHAO</name><affiliation wicri:level="1"><inist:fA14 i1="02"><s1>Intel Corporation</s1><s2>Santa Clara, CA 95054-1549</s2><s3>USA</s3><sZ>3 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>Intel Corporation</wicri:noRegion></affiliation></author><author><name sortKey="Lee, Jack C" uniqKey="Lee J">Jack C. Lee</name><affiliation wicri:level="4"><inist:fA14 i1="03"><s1>Department of Electrical and Computer Engineering, University of Texas at Austin</s1><s2>Austin, TX 78712-0240</s2><s3>USA</s3><sZ>4 aut.</sZ></inist:fA14><country>États-Unis</country><placeName><settlement type="city">Austin (Texas)</settlement><region type="state">Texas</region></placeName><orgName type="university">Université du Texas à Austin</orgName></affiliation></author><author><name sortKey="Veksler, Dmitry" uniqKey="Veksler D">Dmitry Veksler</name><affiliation wicri:level="1"><inist:fA14 i1="04"><s1>SEMATECH</s1><s2>Albany, NY 12203</s2><s3>USA</s3><sZ>5 aut.</sZ><sZ>6 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>SEMATECH</wicri:noRegion></affiliation></author><author><name sortKey="Bersuker, Gennadi" uniqKey="Bersuker G">Gennadi Bersuker</name><affiliation wicri:level="1"><inist:fA14 i1="04"><s1>SEMATECH</s1><s2>Albany, NY 12203</s2><s3>USA</s3><sZ>5 aut.</sZ><sZ>6 aut.</sZ></inist:fA14><country>États-Unis</country><wicri:noRegion>SEMATECH</wicri:noRegion></affiliation></author></titleStmt><publicationStmt><idno type="inist">12-0265833</idno><date when="2012">2012</date><idno type="stanalyst">PASCAL 12-0265833 INIST</idno><idno type="RBID">Pascal:12-0265833</idno><idno type="wicri:Area/Main/Corpus">001C05</idno><idno type="wicri:Area/Main/Repository">001C39</idno></publicationStmt><seriesStmt><idno type="ISSN">0018-9383</idno><title level="j" type="abbreviated">IEEE trans. electron devices</title><title level="j" type="main">I.E.E.E. transactions on electron devices</title></seriesStmt></fileDesc><profileDesc><textClass><keywords scheme="KwdEn" xml:lang="en"><term>Alumina</term><term>Binary compound</term><term>Buried channel</term><term>Charge carrier density</term><term>Coulomb scattering</term><term>Field effect transistor</term><term>Heterostructures</term><term>Indium phosphide</term><term>MOS technology</term><term>MOSFET</term><term>Numerical simulation</term><term>Reference model</term><term>Voltage capacity curve</term></keywords><keywords scheme="Pascal" xml:lang="fr"><term>Canal enterré</term><term>Technologie MOS</term><term>Transistor MOSFET</term><term>Simulation numérique</term><term>Caractéristique capacité tension</term><term>Densité porteur charge</term><term>Diffusion Coulomb</term><term>Modèle référence</term><term>Transistor effet champ</term><term>Hétérostructure</term><term>Alumine</term><term>Phosphure d'indium</term><term>Composé binaire</term><term>Al2O3</term><term>InP</term></keywords></textClass></profileDesc></teiHeader><front><div type="abstract" xml:lang="en">The accuracy of the split-CV mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a Al<sub>2</sub>O<sub>3</sub> gate dielectric and an InP barrier, through a "simulated experiment" procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental I-V and CV curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split-CV method can appreciably underestimate the actual channel mobility in these devices, with an error of > 20% and > 50% on peak mobility and high-V<sub>GS</sub> mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing V<sub>GS</sub>. It is shown that this behavior can be an artifact of the extraction method, which may mask physical mechanisms causing a real mobility drop with decreasing channel carrier density, such as Coulomb scattering mechanisms. This poses limitations to the adoption of split-C V mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V FETs, including both heterostructure-based and inversion-mode devices.</div></front></TEI><inist><standard h6="B"><pA><fA01 i1="01" i2="1"><s0>0018-9383</s0></fA01><fA02 i1="01"><s0>IETDAI</s0></fA02><fA03 i2="1"><s0>IEEE trans. electron devices</s0></fA03><fA05><s2>59</s2></fA05><fA06><s2>4</s2></fA06><fA08 i1="01" i2="1" l="ENG"><s1>Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs</s1></fA08><fA11 i1="01" i2="1"><s1>MORASSI (Luca)</s1></fA11><fA11 i1="02" i2="1"><s1>VERZELLESI (Giovanni)</s1></fA11><fA11 i1="03" i2="1"><s1>HAN ZHAO</s1></fA11><fA11 i1="04" i2="1"><s1>LEE (Jack C.)</s1></fA11><fA11 i1="05" i2="1"><s1>VEKSLER (Dmitry)</s1></fA11><fA11 i1="06" i2="1"><s1>BERSUKER (Gennadi)</s1></fA11><fA14 i1="01"><s1>Department of Engineering Sciences and Methods, University of Modena and Reggio Emilia</s1><s2>42122 Reggio Emilia</s2><s3>ITA</s3><sZ>1 aut.</sZ><sZ>2 aut.</sZ></fA14><fA14 i1="02"><s1>Intel Corporation</s1><s2>Santa Clara, CA 95054-1549</s2><s3>USA</s3><sZ>3 aut.</sZ></fA14><fA14 i1="03"><s1>Department of Electrical and Computer Engineering, University of Texas at Austin</s1><s2>Austin, TX 78712-0240</s2><s3>USA</s3><sZ>4 aut.</sZ></fA14><fA14 i1="04"><s1>SEMATECH</s1><s2>Albany, NY 12203</s2><s3>USA</s3><sZ>5 aut.</sZ><sZ>6 aut.</sZ></fA14><fA20><s1>1068-1075</s1></fA20><fA21><s1>2012</s1></fA21><fA23 i1="01"><s0>ENG</s0></fA23><fA43 i1="01"><s1>INIST</s1><s2>222F3</s2><s5>354000505249000260</s5></fA43><fA44><s0>0000</s0><s1>© 2012 INIST-CNRS. All rights reserved.</s1></fA44><fA45><s0>17 ref.</s0></fA45><fA47 i1="01" i2="1"><s0>12-0265833</s0></fA47><fA60><s1>P</s1></fA60><fA61><s0>A</s0></fA61><fA64 i1="01" i2="1"><s0>I.E.E.E. transactions on electron devices</s0></fA64><fA66 i1="01"><s0>USA</s0></fA66><fC01 i1="01" l="ENG"><s0>The accuracy of the split-CV mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a Al<sub>2</sub>O<sub>3</sub> gate dielectric and an InP barrier, through a "simulated experiment" procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental I-V and CV curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split-CV method can appreciably underestimate the actual channel mobility in these devices, with an error of > 20% and > 50% on peak mobility and high-V<sub>GS</sub> mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing V<sub>GS</sub>. It is shown that this behavior can be an artifact of the extraction method, which may mask physical mechanisms causing a real mobility drop with decreasing channel carrier density, such as Coulomb scattering mechanisms. This poses limitations to the adoption of split-C V mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V FETs, including both heterostructure-based and inversion-mode devices.</s0></fC01><fC02 i1="01" i2="X"><s0>001D03F04</s0></fC02><fC02 i1="02" i2="X"><s0>001D03F02</s0></fC02><fC03 i1="01" i2="X" l="FRE"><s0>Canal enterré</s0><s5>01</s5></fC03><fC03 i1="01" i2="X" l="ENG"><s0>Buried channel</s0><s5>01</s5></fC03><fC03 i1="01" i2="X" l="SPA"><s0>Canal enterrado</s0><s5>01</s5></fC03><fC03 i1="02" i2="X" l="FRE"><s0>Technologie MOS</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="ENG"><s0>MOS technology</s0><s5>02</s5></fC03><fC03 i1="02" i2="X" l="SPA"><s0>Tecnología MOS</s0><s5>02</s5></fC03><fC03 i1="03" i2="3" l="FRE"><s0>Transistor MOSFET</s0><s5>03</s5></fC03><fC03 i1="03" i2="3" l="ENG"><s0>MOSFET</s0><s5>03</s5></fC03><fC03 i1="04" i2="X" l="FRE"><s0>Simulation numérique</s0><s5>04</s5></fC03><fC03 i1="04" i2="X" l="ENG"><s0>Numerical simulation</s0><s5>04</s5></fC03><fC03 i1="04" i2="X" l="SPA"><s0>Simulación numérica</s0><s5>04</s5></fC03><fC03 i1="05" i2="X" l="FRE"><s0>Caractéristique capacité tension</s0><s5>05</s5></fC03><fC03 i1="05" i2="X" l="ENG"><s0>Voltage capacity curve</s0><s5>05</s5></fC03><fC03 i1="05" i2="X" l="SPA"><s0>Característica capacidad tensión</s0><s5>05</s5></fC03><fC03 i1="06" i2="X" l="FRE"><s0>Densité porteur charge</s0><s5>06</s5></fC03><fC03 i1="06" i2="X" l="ENG"><s0>Charge carrier density</s0><s5>06</s5></fC03><fC03 i1="06" i2="X" l="SPA"><s0>Concentración portador carga</s0><s5>06</s5></fC03><fC03 i1="07" i2="X" l="FRE"><s0>Diffusion Coulomb</s0><s5>07</s5></fC03><fC03 i1="07" i2="X" l="ENG"><s0>Coulomb scattering</s0><s5>07</s5></fC03><fC03 i1="07" i2="X" l="SPA"><s0>Difusión Coulomb</s0><s5>07</s5></fC03><fC03 i1="08" i2="X" l="FRE"><s0>Modèle référence</s0><s5>08</s5></fC03><fC03 i1="08" i2="X" l="ENG"><s0>Reference model</s0><s5>08</s5></fC03><fC03 i1="08" i2="X" l="SPA"><s0>Modelo referencia</s0><s5>08</s5></fC03><fC03 i1="09" i2="X" l="FRE"><s0>Transistor effet champ</s0><s5>09</s5></fC03><fC03 i1="09" i2="X" l="ENG"><s0>Field effect transistor</s0><s5>09</s5></fC03><fC03 i1="09" i2="X" l="SPA"><s0>Transistor efecto campo</s0><s5>09</s5></fC03><fC03 i1="10" i2="3" l="FRE"><s0>Hétérostructure</s0><s5>10</s5></fC03><fC03 i1="10" i2="3" l="ENG"><s0>Heterostructures</s0><s5>10</s5></fC03><fC03 i1="11" i2="X" l="FRE"><s0>Alumine</s0><s2>NK</s2><s5>22</s5></fC03><fC03 i1="11" i2="X" l="ENG"><s0>Alumina</s0><s2>NK</s2><s5>22</s5></fC03><fC03 i1="11" i2="X" l="SPA"><s0>Alúmina</s0><s2>NK</s2><s5>22</s5></fC03><fC03 i1="12" i2="X" l="FRE"><s0>Phosphure d'indium</s0><s5>23</s5></fC03><fC03 i1="12" i2="X" l="ENG"><s0>Indium phosphide</s0><s5>23</s5></fC03><fC03 i1="12" i2="X" l="SPA"><s0>Indio fosfuro</s0><s5>23</s5></fC03><fC03 i1="13" i2="X" l="FRE"><s0>Composé binaire</s0><s5>24</s5></fC03><fC03 i1="13" i2="X" l="ENG"><s0>Binary compound</s0><s5>24</s5></fC03><fC03 i1="13" i2="X" l="SPA"><s0>Compuesto binario</s0><s5>24</s5></fC03><fC03 i1="14" i2="X" l="FRE"><s0>Al2O3</s0><s4>INC</s4><s5>82</s5></fC03><fC03 i1="15" i2="X" l="FRE"><s0>InP</s0><s4>INC</s4><s5>83</s5></fC03><fC07 i1="01" i2="X" l="FRE"><s0>Composé III-VI</s0><s5>11</s5></fC07><fC07 i1="01" i2="X" l="ENG"><s0>III-VI compound</s0><s5>11</s5></fC07><fC07 i1="01" i2="X" l="SPA"><s0>Compuesto III-VI</s0><s5>11</s5></fC07><fC07 i1="02" i2="X" l="FRE"><s0>Composé III-V</s0><s5>12</s5></fC07><fC07 i1="02" i2="X" l="ENG"><s0>III-V compound</s0><s5>12</s5></fC07><fC07 i1="02" i2="X" l="SPA"><s0>Compuesto III-V</s0><s5>12</s5></fC07><fN21><s1>198</s1></fN21><fN44 i1="01"><s1>OTO</s1></fN44><fN82><s1>OTO</s1></fN82></pA></standard></inist></record>Pour manipuler ce document sous Unix (Dilib)
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